module FA( InA, InB, CarryIn, Sum, CarryOut );
input InA, InB, CarryIn;
output Sum, CarryOut;
reg Sum, CarryOut;
always @ (*)
begin
{CarryOut,Sum} = InA+ InB+CarryIn;
end
endmodule
module alu0( A, B, Binvert, CarryIn, Operation, CarryOut, Result, less );
input A, B, Binvert, CarryIn, Operation, less;
output CarryOut, Result;
reg Result;
wire CarryOut, B_Sel;
FA FA_0( .Sum(FA_Sum), .CarryIn(CarryIn), .InA(A), .InB(B), .CarryOut(CarryOut) );
assign B_Sel = (Binvert==0) ? B : ~B;
always @(*)
begin
case(Operation)
0:
Result <= A & B_Sel;
1:
Result <= A | B_Sel;
2:
Result <= FA_Sum;
3:
Result <= less;
default:
Result <= 0;
endcase
end
endmodule
module alu1( A, B, Binvert, CarryIn, Operation, Result, less, Set, Overflow );
input A, B, Binvert, CarryIn, Operation, less;
output Result, Set, Overflow;
reg Result, Set, Overflow;
wire CarryOut, B_Sel;
FA FA_0( .Sum(FA_Sum), .CarryIn(CarryIn), .InA(A), .InB(B), .CarryOut(CarryOut) );
assign B_Sel = (Binvert==0) ? B : ~B;
always @(*)
begin
case(Operation)
0:
Result <= A & B_Sel;
1:
Result <= A | B_Sel;
2:
Result <= FA_Sum;
3:
Result <= less;
default:
Result <= 0;
endcase
end
always@(*)
begin
Set <= FA_Sum;
Overflow <= CarryIn ^ CarryOut;
end
endmodule
module ALU_top( InA, InB, Binvert, Operation, Result, Zero, Overflow );
parameter width = 32;
input [width-1:0] InA, InB;
input Binvert;
input [1:0] Operation;
output [width-1:0] Result;
output Zero, Overflow;
wire Set, ov;
wire [width-1:0] CarryOut;
alu0 alu_fs( .A(InA[0]), .B(InB[0]),
.Binvert(Binvert), .CarryIn(Binvert),
.Operation(Operation), .CarryOut(CarryOut[0]),
.Result(Result[0]), .less(Set) );
genvar i;
generate for ( i = 1; i < 31; i=i+1 )
begin:gs1
alu0 alu_gs1( .A(InA[i]), .B(InB[i]),
.Binvert(Binvert), .CarryIn(CarryOut[i-1]),
.Operation(Operation), .CarryOut(CarryOut[i]),
.Result(Result[i]), .less(1'b0) );
end
endgenerate
alu1 alu_fi( .A(InA[31]), .B(InB[31]),
.Binvert(Binvert), .CarryIn(CarryOut[30]),
.Operation(Operation),
.Result(Result[31]), .less(1'b0),
.Set(Set), .Overflow(Overflow) );
assign ov = |Result;
assign Zero = ~ov;
endmodule
// 하면서 고민했던거 고찰에 적어넣으면 됨.
